1. Field of the Invention
The present invention relates to a semiconductor device including an antifuse and a manufacturing method of the semiconductor device.
Note that a semiconductor device in this specification refers to all devices which can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic appliances are all semiconductor devices.
2. Description of the Related Art
A ROM (read only memory), which performs only reading, is classified into a mask ROM and a PROM (programmable ROM). A fuse ROM and an antifuse ROM are a kind of PROM. The mask ROM is a ROM to which information is written using a photomask in a manufacturing process. The fuse ROM is a ROM in which a fuse which is in a conductive state at the time of manufacture is used for a memory element and the fuse is disconnected by current after the manufacture to make electrodes of the fuse electrically disconnected, whereby information is stored. On the other hand, the antifuse ROM is a ROM in which an antifuse which is in a nonconductive state at the time of manufacture is used for a memory element and electrodes of the antifuse are electrically connected by current after the manufacture, whereby information is written thereto. For example, an antifuse using silicon or germanium is described in Patent Document 1 (Japanese Published Patent Application No. H7-297293), Patent Document 2 (Japanese Published Patent Application No. H6-260558), Patent Document 3 (Japanese Published Patent Application No. H5-343633), Patent Document 4 (Japanese Published Patent Application No. H4-282864), and Patent Document 5 (Japanese Published Patent Application No. 114-226068).
In Patent Document 1, an antifuse in which amorphous silicon is interposed between a pair of conductors is described. In Patent Document 1, one of electrodes is formed of a metal, and the amorphous silicon and the metal are made to react with each other to form silicide, whereby the antifuse is placed in a conductive state.
According to Patent Document 1, when a silicide reaction rate is set to greater than or equal to 10 m/sec, variation in resistance values of the antifuse which has been placed in the conductive state and malfunction of the antifuse which has been placed in the conductive state can be suppressed, and realization of the reaction rate of greater than or equal to 10 m/sec results from an effect of not exposing a surface on which the amorphous silicon and the metal are to be formed to an oxygen atmosphere like the air between a formation step of the amorphous silicon and a formation step of the metal. Therefore, in Patent Document 1, the antifuse is manufactured in such a manner that the metal film, the amorphous silicon, and the metal film are continuously formed without being exposed to the air in a multi-chamber system.
In Patent Document 2, an antifuse constituted by aluminum and germanium which is in contact with the aluminum is described.
An antifuse described in Patent Document 3 has a structure in which an amorphous silicon film containing germanium is interposed between wirings. According to Patent Document 3, writing voltage can be lowered by adjustment of content percentage of germanium in the amorphous silicon film.
In Patent Document 4, an antifuse constituted by an electrode; a conductor formed of silicon nitrides; an amorphous silicon layer over the conductor; a conductor formed of silicon nitrides, which is over the amorphous silicon; and an electrode over the conductor is described.
In Patent Document 5, an antifuse constituted by an electrode formed of a heat-resistant metal layer and a titanium layer; a conductor layer over the electrode; an amorphous silicon layer over the conductor layer; and an electrode over the amorphous silicon layer is described.